DFT Engineer

Full Time
Posted 2 weeks ago

Company specializes in providing embedded systems, silicon solutions, related services and having strong partnerships with top players in the Semiconductor and Embedded Systems domain, across product development and prototyping is looking for suitable Engineers.


The role encompasses a multifaceted approach to DFT (Design-for-Testability), involving architecture definition, logic design, verification, test pattern generation, chip bring-up, and more. This is an opportunity to work on cutting-edge technologies in silicon chip design within a dynamic, open, and fast-paced environment, shaping the future of chips for our top-notch clients.

As a Senior DFT Engineer, you will play a crucial role throughout the device lifecycle, from the definition
stage to mass production. Working closely with various VLSI engineering groups, including chip design,
verification, backend, test, and reliability, you will be responsible for developing, implementing, and
verifying Design for Testability (DFT) on complex System on Chips (SOCs). This role involves
collaboration with the architecture team to understand DFT architecture, ensuring DFT design rules
compliance with the design teams, and working with the physical design team to meet DFT
requirements. The ideal candidate will have expertise in SOC-level DFT techniques, ATPG, MBIST, JTAG,
and boundary scan.

• 6+ years chip design experience.
• 4+ years as a DFT engineer in a semiconductor company.
• Bachelor’s/Master’s in Electrical/Electronics Engineering.
• Strong post-silicon DFT bring-up and debug experience.
• Hands-on experience with multi-vendor DFT tools.
• Proficiency in ATPG tools (Mentor TK).
• Exposure to static timing analysis; timing closure.
• Excellent scripting skills in Perl/Tcl/Tk/Python.
• Knowledge of DFT technologies (JTAG, MBIST, Scan).
• Experience with RTL Coding (Verilog, System Verilog, VHDL).
• Strong communication, teamwork, and leadership skills.
• Expertise in DFT methodologies (scan insertion, scan compression, boundary scan, memory
• Experience with DFT tools (Tessent, ATPG, MBIST, JTAG).
• Proficiency in Shell/Perl/Tcl and other scripting languages.
• Familiarity with ATE. Chip design, Verilog, and System Verilog.
• Verification, UVM methodology.
• ATPG tools, scan insertion tools, gate-level simulations.
• Static timing analysis.
• Scripting (Perl/Tcl).
• Energetic, self-motivated.
• Proactive, detail-oriented, and quality-focused.
• Team player with strong communication and reporting skills.
• Ability to collaborate with overseas partners.

Work Location : Bangalore

CTC : 30.0 LPA

Interested candidates please call us on 9035007003/9845264304/9035302302 or email resume to : placements@beechi.in

Job Features

Job CategoryIT

Apply Online

A valid email address is required.
A valid phone number is required.