Company specializes in providing embedded systems, silicon solutions, related services and having strong partnerships with top players in the Semiconductor and Embedded Systems domain, across product development and prototyping is looking for exceptional engineers and engineering leaders to join SOC development team to develop cutting-edge products within disruptive system architecture.
You will have the opportunity to work on the latest technologies in silicon chip design within a dynamic, open, and fast-paced environment and develop the next generation of chips based on revolutionary architecture for our top-notch clients.
We are looking for talented Senior engineers to join our top-tier teams and participate in design and verification activities working on next-generation products, starting from the identification and definition of project requirements, architecture, and feature development. As a Senior Chip Design engineer and a member of the project team, you will work in close collaboration with cross-functionals teams, including
Architecture, Software, Verification, Backend, DFT, and more, and will have an opportunity to create an impact at scale throughout the entire product lifecycle.
In this role, you will work in a team developing SoCs to be deployed in a range of products/applications. You will integrate industry-standard and custom hardware IP and subsystems into SoCs and will work closely with System Architects, SoC architects, IP developers, and physical design teams to develop SoCs that meet the power, performance, and area goals for these products/applications.
6+ years of experience in chip design.
5+ years or more of practical semiconductor design experience.
Proficiency in Verilog/System Verilog.
Fluent in scripting languages (C*, Perl, Python, TCL).
BE degree in Computer Engineering/BS Computer Science/Electrical Engineering.
Excellent verbal and written communication skills.
Strong collaboration and teamwork skills, ability to contribute to diverse and inclusive teams.
Experience with the full SOC cycle – Synthesis/STA/CDC/Lint.
Experience with successful tape-outs of complex, high- volume SoCs in advanced design nodes.
Experience with Design Automation.
Experience in Designing protocols such as PCIE, DDR, CHI, AMBA.
Strong working knowledge of Network on Chip (NOC), Coherent, and non-Coherent fabrics.
A higher degree in a technically related field is an advantage.
Work Location : Bangalore
CTC : 30.0 LPA
Interested candidates please call us on 9035007003/9845264304/9035302302 or email resume to : firstname.lastname@example.org